Learn VHDL and FPGA Development

Learn VHDL and FPGA Development

English | MP4 | AVC 1280×720 | AAC 48KHz 2ch | 11 Hours | 1.95 GB

Learn how to create a VHDL design that can be simulated and implemented on a Xilinx or Altera FPGA development board.

This course supports both the Xilinx and Altera FPGA development boards.

VHDL and FPGA Development for Beginners and Intermediates is a course that is designed to teach students how to create and successfully simulate their VHDL design. We will also be implementing these designs on a Xilinx BASYS 3 or BASYS 2 FPGA development board so that the students can see their designs actually running. This course starts from beginning to end in teaching the user how to turn their digital logic design into VHDL designs that can be simulated in ModelSim or ISim and then implemented on an FPGA development board. This course also covers how to use Altera’s tools so students are not limited to Xilinx development boards.

Course Structure:

This course contains over 20 lectures that will teach students the syntax and structure of VHDL. The student will be able to understand the syntax and use of specific VHDL keywords by taking this course. There are lectures included in each lab to give a background on the digital logic circuit the student will be implementing.

This course contains 7 labs that are designed so that the student will learn how to develop VHDL code. For each lab I will give the student a set of VHDL files that they will have to modify or change in order to get the project to simulate correctly in ModelSim and so they can implement the design on their FPGA board. These labs are design to help the students learn VHDL by actually coding it themselves.

What Will I Learn?

  • Understand the design process for implementing a digital design onto a FPGA
  • Learn how to simulate a design in Altera’s ModelSim and Xilinx Isim
  • Learn how to use Xilinx ISE tool to program FPGA
  • Debug a VHDL design using ModelSim
  • Simulate a VHDL design using ModelSim
  • Familiarize yourself with Altera and Xilinx tools
  • Program a FPGA
Table of Contents

Contact Information
1 Contact Information
2 Extra Resources for Using FPGAs

Introduction
3 Introduction to the Course
4 Introduction to VHDL

VHDL Data Types
5 Data Types Introduction
6 Signals Variables Constants
7 Unsigned Signed Data Types
8 Standard Logic Vector Standard Logic
9 Integer Boolean Data Types
10 Initializing Values in VHDL
11 Data Type Examples in VHDL Designs Part 1
12 Data Type Examples in VHDL Designs Part 2

VHDL Syntax
13 VHDL Syntax Introduction
14 If Statement Case Statement
15 For Loop While Loop
16 VHDL For Loop Example
17 When Else Statement With Select When Statement
18 VHDL Processes and Concurrent Statement
19 VHDL Syntax Design Example
20 1 VHDL Basics

VHDL Coding Structure
21 Organizing Your VHDL Designs
22 VHDL Design Structure
23 VHDL Design Architecture Styles
24 Data Flow Architecture Example – Full Adder
25 Behavioral Architecture Example – Full Adder
26 Concept of VHDL Modeling
27 VHDL Coding Structure

Test Bench
28 Test Benches Introduction
29 Test Bench Structure Walkthrough
30 Walkthrough of a Completed Test Bench
31 VHDL Test Benches

Implementing State Machines in VHDL
32 State Machine Introduction
33 Designing a State Machine

FPGA Development Boards
34 Supported FPGA Development Boards
35 BASYS 3 Board Overview
36 BASYS 3 Board User Guide
37 BASYS 3 Board Schematic
38 BASYS 2 Board
39 BASYS 2 Board User Guide
40 BASYS 2 Board Schematic
41 BASYS 2 Board Overview

Altera Tools
42 Altera Tools Introduction
43 ModelSim VHDL Simulation Tool
44 Quartus II FPGA Development Tool
45 Altera Tools

Xilinx Tools
46 Xilinx Tools Introduction
47 Download the Vivado Tool Suite for the BASYS 3
48 ISim VHDL Simulation Tool
49 Xilinx ISE FPGA Development Tool
50 Programming The BASYS 2 FPGA Development Board
51 Xilinx Tools

Lab 1 – Full Adder
52 Introduction
53 BASYS 3 Full Adder Demonstration
54 BASYS 2 Full Adder Demonstration
55 BASYS 2 Full Adder Solution

Lab 2 – Shift Register
56 Introduction
57 BASYS 3 Shift Register Demonstration
58 BASYS 2 Shift Register Demonstration
59 Shift Register Completed Design

Lab 3 – Universal Shift Register
60 Introduction
61 BASYS 3 Universal Shift Register Demonstration
62 BASYS 2 Universal Shift Register Demonstration
63 BASYS 2 Universal Shift Register Solution
64 Universal Shift Register VHDL Design

Lab 4 – 7 Segment Display
65 Introduction
66 BASYS 3 – 7 Segment Display Demonstration
67 BASYS 2 – 7 Segment Display Demonstration
68 Hexadecimal to 7 Segment Display VHDL Design

Lab 5 – Counter
69 Introduction
70 BASYS 3 Counter Demonstration
71 BASYS 2 Counter Demonstration
72 Counter VHDL Design

Lab 6 – Multiplier
73 Introduction
74 BASYS 3 Multiplier Demonstration
75 BASYS 2 Multiplier Demonstration
76 Multiplier VHDL Design File

Lab 7 – RC Servo
77 Introduction
78 BASYS 3 RC Servo Demonstration
79 BASYS 2 RC Servo Demonstration
80 RC Servo VHDL Design Files

Lecture Notes
81 Introduction to VHDL Notes
82 Data Types Notes
83 Syntax Notes
84 Structure Notes
85 Coding Styles Notes
86 Test Benches Notes
87 Altera Tools Notes
88 ModelSim Notes
89 Quartus II Notes
90 Xilinx Tools Notes
91 Isim Notes
92 Xilinx ISE Project Notes
93 Programming BASYS Board
94 BASYS 2 Board Notes

Extra References
95 Free Range VHDL Notes
96 VHDL Cookbook